Improved Design of Low Power TPG using LPLFSR

Authors:AJMEERAA KISHAN, DANTHAMALA KOTESHWAR RAO

0616-0619

Design of Low Power High Speed Flash ADC in 45nm CMOS

Authors:NABEEL P S1, T E AYOOB KHAN, DR. SHAHUL HAMEED T A

0620-0625

Distributed Arithmetic Method with Eight Parallel Computation Paths Used Effective Multi Standard Supporting the Standards MPEG, H.264 and VC-1

Authors:T. SINDHU PRIYA, S. RANJITH KUMAR

0626-0630

Designing of Convolutional Encoder & Adaptive Viterbi Decoder using Verilog

Authors:S. RAVI PRAKASH, L M L NARAYANA REDDY

0631-0634

Conventional TSPC Based Prescaler Implementation using Low Power Single Phase Clock Distribution

Authors:K.ANUSHA 1, VELPULA RAMBABU, KOTA VENKATESWARA RAO

0635-0639

FPGA Implementation Based on 32-Point FFT using Radix-2 Algorithm

Authors:B.USHARANI, KOTA VENKATESWARA RAO

0640-0644

Implementation of High Speed 8-Bit Vedic Multiplier Based on FPGA using Barrel Shifter

Authors:SREENUBABU, VELPULA RAMBABU, KOTA VENKATESWARA RAO

0645-0649

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC

Authors:MANOJKUMAR REDDY. NALI, SHAIK. JAMEER

0650-0655

Implementation of a Fixed Hardware Structure Used for Built-In Generation of Functional Broadside Tests with Low Power

Authors:SHAHLA REEM, CH. SAMBA RAJU

0656-0659

Secured Data Aggregation Network in Wireless Sensor

Authors:JABER IBRAHIM NASER, O. SUBHASH CHANDER GOUD

0660-0670